1. Field of the Invention
This invention relates to a semiconductor device, and, more particularly, to the reducing the area of a semiconductor chip that is occupied by wiring.
2. Description of the Related Art
In recent years, the amount of wiring used for signal lines, data lines, and so forth, has increased significantly as a result of the increase in capacity of and the multiple functions now performed by semiconductor devices.
FIG. 1, for example, shows a block diagram of a row address designation section of a prior art dynamic random access memory (DRAM). Referring to FIG. 1, n row address signals A0 to An-1 (n: an integer) are respectively input to n address pads 11. N address pads 11 are respectively connected to n row address buffers 12. Address buffers 12 respectively receive the row address signals input to associated address pads 11, and each generate two complementary address signals, i.e., an address signal at the same logic level as that of the input row address signal, and an address signal opposite in level to that of the input row address signal. In other words, buffers 12 each generate two address signals, one at a positive logic level, and the other at a negative logic level. These address signals are input to row decoder 14 via row address signal lines 13. Row address decoder 14 decodes the address signals, and from among a plurality of word lines 15 of memory cell array 16 which are connected to the output terminals of row decoder 14, selects and energizes the one of these word lines which has been designated by the decoded address signal.
FIG. 2 shows a circuit configuration illustrating a row address buffer of a typical conventional DRAM.
The row address buffer includes P channel enhancement type MOS (metal oxide semiconductor) transistors Q1 to Q4 and N channel enhancement type MOS transistors Q5 to Q12. The main portion of the row address buffer includes a flip-flop circuit, which is made up of P channel MOS transistors Q1 to Q4 and N channel transistors Q5 to Q10. The source of P channel MOS transistor Q1 is connected to a power potential of 5 V, and its drain is connected to the drain of N channel MOS transistor Q5. The source of N channel MOS transistor Q5 is supplied with clock pulse .phi.3 (FIG. 3) via a control signal line. The source of P channel MOS transistor Q2 is also connected to the power potential of 5 V, and its drain is connected to the drain of N channel MOS transistor Q6. The source of N channel MOS
transistor Q6 is also supplied with clock pulse .phi.3. The connection point of the drains of P channel MOS transistor Q1 and N channel MOS transistor Q5 is itself connected to the gate of P channel MOS transistor Q2, and also to the gate of N channel MOS transistor Q6. Likewise, the connection point of the drains of P channel MOS transistor Q2 and N channel MOS transistor Q6 is connected to the gate of P channel MOS transistor Q1, and also to the gate of N channel MOS transistor Q5.
P channel MOS transistor Q3 and N channel MOS transistors Q7 and Q9 are connected in series between the power potential of 5 V and the ground potential. P channel MOS transistor Q4 and N channel MOS transistors Q8 and Q10 are similarly connected in series between these same potentials. The gate of N channel MOS transistor Q7 is connected to address pad 11 via N channel MOS transistor Q11, which acts as a transfer gate. The gate of N channel MOS transistor Q8 is supplied with reference potential VREF via N channel MOS transistor and Q12, which acts as a transfer gate. Clock pulse .phi.1 (FIG. 3) is supplied to the gates of N channel MOS transistors Q9 and Q10, and clock pulse .phi.2 (FIG. 3) is supplied to the gates of N channel MOS transistors Q11 and Q12, both of which act as transfer gates. The gates of P channel MOS transistors Q3 and Q4 are grounded.
Next, the operation of the row address buffer of FIG. 2 will be described.
The address buffer is operated under the control of clock pulses.
Assume that clock pulse .phi.2 is at a high level, and N channel MOS transistors 011 and Q12, acting as transfer gates, are in an on-state. Under these conditions, if clock pulse .phi.1 goes high in level and N channel MOS transistors Q9 and Q10 are turned on, the comparison of the potential of the address signal input via address pad 11 with reference potential VREF is started. Specifically, the comparison of the potential at the connection point of the drains of P channel MOS transistor Q1 and N channel MOS transistor Q5 with the potential at the connection point of the drains of P channel MOS transistor Q2 and N channel MOS transistor Q8, is started by the flip-flop. Subsequently, if clock pulse .phi.2 goes low, N channel MOS transistors Q11 and Q12 are turned off, and the row address buffer is disconnected from the external circuit. That is, the row address buffer is disconnected from the external address signal potential and reference potential VREF. If then, clock pulse .phi.3 goes low, it is decided which of the address signal potential and reference potential VREF is higher. If the address signal potential is higher than reference potential VREF, the address signal potential is determined to be at a high level. Conversely, if the address signal potential is lower than reference potential VREF, the address signal potential is determined to be at a low level. If the address signal potential is high, the data of the flip-flop is inverted.
FIG. 4 shows a block diagram illustrating the FIG. 2 row address buffer and the row address buffer control circuit. As shown in FIG. 4, three control signal lines are necessary for introducing control signals .phi.1, .phi.2 and .phi.3 from row address buffer control circuit 22 to row address buffer 21.
In the prior semiconductor device shown in FIG. 1, 2n row address signal lines are formed on the semiconductor chip for n row address signals. On the semiconductor chip, the distance between the the address signal buffer and the row decoder is large, so that the wiring occupies a large area on the semiconductor chip. Reduction of the wiring area narrows the width of wiring and the intervals among the wirings. This makes it difficult to manufacture the semiconductor device.
The semiconductor devices shown in FIGS. 2 and 4 need each three control lines. For this reason, as in the semiconductor device shown in FIG. 1, the wiring area on the chip is large. Reduction of the wiring area narrows the width of wirings and the intervals between the wirings. This makes it difficult to fabricate the semiconductor device.
In the future, the capacity of the semiconductor devices will be increased, and the single semiconductor device thus operate in a multi-function manner. With this trend, the number of address signal lines and the control signal lines will also be increased. This necessitates a further reduction of the wiring width and the inter-wire interval, providing a more difficult technical problem in fabricating the semiconductor devices.